Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
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Synopsis

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Derechos de autor:
2014 Springer

Book Details

Book Quality:
ISBN-13:
9783319023786
Publisher:
Springer International Publishing, Cham
Date of Addition:
Idioma:
English
Categorías:
Nonfiction, Technology,
Usage Restrictions:
This is a copyrighted book.